In a manufacturing process of a semiconductor device, a mask having a preset pattern is formed on an etching target layer, and the pattern of the mask is transcribed to the etching target layer by etching. For example, a resist mask formed by a photolithography technique is used as the mask. Accordingly, a limit size of the pattern formed on the etching target layer is affected by a resolution limit of the resist mask formed by the photolithography technique.
Along with the recent trend of miniaturization and high integration of semiconductor devices, a photolithography technique using an EUV (Extreme Ultra-Violet) light having a wavelength shorter than that of an ArF excimer laser beam is being considered. The photolithography using the EUV light enables forming a finer pattern on the resist mask, as compared to the photolithography using the ArF excimer laser beam. In the photolithography using the EUV light, a fine processing of, e.g., 10 nm or less can be performed.
With regard to the pattern formed on the resist mask, if a ratio of a height of the resist mask to a pattern size thereof is equal to or larger than 3, a problem such as a pattern collapse may be caused. In view of this, the ratio of the height of the resist mask to the pattern size thereof needs to be set to be equal to or less than 3. If the semiconductor device is miniaturized, the height of the resist mask is also thinned. The height of the resist mask becomes, for example, equal to or less than 30 nm in the generation of 10 nm.
When the etching target layer is etched, a part of the resist mask is also etched. If the height of the resist mask is thinned, however, the preset pattern of the resist mask cannot be maintained until the preset pattern is formed on the etching target layer. Accordingly, accuracy of a size of the pattern formed on the etching target layer after being etched may be degraded.
Described in Patent Document 1 is a technique of forming an encapsulation layer on a resist on a pattern and then performing an etching process for patterning a hard mask in order to improve etching resistance of an EUV photoresist. Further, in Patent Document 2, it is described that a wafer temperature is controlled to −40° C. to 0° C. only in a process of etching an organic antireflection film by using an ArF resist having a preset pattern as a mask in order to suppress a damage of the resist.
Patent Document 1: Japanese Patent Laid-open Publication No. 2013-145874
Patent Document 2: Japanese Patent Laid-open Publication No. 2005-072518